cystech electronics corp. spec. no. : c918e3 issued date : 2013.06.10 revised date : page no. : 1/8 MTE05N08E3 cystek product specification n-channel enhancement mode power mosfet MTE05N08E3 bv dss 80v i d 180a r dson(typ) @ v gs =10v, i d =20a 4.3m r dson(typ) @ v gs =7v, i d =20a 4.5m features ? low gate charge ? simple drive requirement ? repetitive avalanche rated ? fast switching characteristic ? rohs compliant package symbol outline MTE05N08E3 to-220 g gate d drain s source ordering information device package shipping to-220 (pb-free lead plating package) 50 pcs/tube, 20 tubes/box, 4 boxes / carton MTE05N08E3-0-ub-s
cystech electronics corp. spec. no. : c918e3 issued date : 2013.06.10 revised date : page no. : 2/8 MTE05N08E3 cystek product specification absolute maximum ratings (t c =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 80 gate-source voltage v gs 25 v continuous drain current @ t c =25 c (note 1) 180 continuous drain current @ t c =100c (note 1) i d 127 pulsed drain current (note 3) i dm 500 continuous drain current @ t a =25 c (note 2) 14 continuous drain current @ t a =70 c (note 2) i dsm 11 avalanche current (note 3) i as 30 a avalanche energy @ l=0.1mh, i d =90a, r g =25 (note 2) e as 405 repetitive avalanche energy@ l=0.1mh (note 3) e ar 33 mj t c =25 c (note 1) 333 power dissipation t c =100 c (note 1) p d 167 w t a =25 c (note 2) 2 power dissipation t a =70 c (note 2) p dsm 1.3 w operating junction and storage temperature tj, tstg -55~+175 c thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 0.45 c/w thermal resistance, junction-to-ambient, max, t 10s (note 1) 15 c/w thermal resistance, junction-to-ambient, max (note 1) r th,j-a 62.5 c/w note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depend s on the user?s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. 3 . repetitive rating, pulse width limited by junction temperature t j(max) =175 c. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4. the maximum current limited by package is 120a. 5. the static characteristics are obtained using <300 s pulses, duty cycl e 0.5% maximum. 6. the r ja is the sum of thermal resistance from junction to case r jc and case to ambient.
cystech electronics corp. spec. no. : c918e3 issued date : 2013.06.10 revised date : page no. : 3/8 MTE05N08E3 cystek product specification characteristics (t c =25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 80 - - v gs =0v, i d =250 a v gs(th) 2.0 2.9 4.0 v v ds = v gs , i d =250 a g fs - 57 - s v ds =5v, i d =20a i gss - - 100 na v gs = 30 - - 10 v ds =80v, v gs =0v i dss - - 50 a v ds =80v, v gs =0v, tj=55 c - 4.3 5.2 v gs =10v, i d =20a *r ds(on) - 4.5 5.5 m v gs =7v, i d =20a dynamic *qg - 120 - *qgs - 32 - *qgd - 42 - nc i d =20a, v ds =40v, v gs =10v *t d(on) - 33 - *tr - 41 - *t d(off) - 90 - *t f - 64 - ns v ds =40v, i d =20a, v gs =10v, r g =3 ciss - 6377 - coss - 702 - crss - 520 - pf v gs =0v, v ds =40v, f=1mhz source-drain diode *i s - - 180 a *v sd - 0.64 1 v i s =1a, v gs =0v *trr - 32 - ns *qrr - 142 - nc i f =20a, v gs =0, di/dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c918e3 issued date : 2013.06.10 revised date : page no. : 4/8 MTE05N08E3 cystek product specification typical characteristics typical output characteristics 0 50 100 150 200 250 300 350 0246810 v ds , drain-source voltage(v) i d , drain current(a) 10v,9v,8v,7v,6v v gs =5v v gs =4 v v gs =6v brekdown voltage vs junction temperature 0.4 0.6 0.8 1 1.2 1.4 -60 -20 20 60 100 140 180 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =6v v gs =7v v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 04812162 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 0 10 20 30 40 50 60 70 80 90 100 024681 0 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -60 -40 -20 0 20 40 60 80 100 120 140 160 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =20a r ds( on) @tj=25c : 4.1m v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =20a
cystech electronics corp. spec. no. : c918e3 issued date : 2013.06.10 revised date : page no. : 5/8 MTE05N08E3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 100000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -60 -20 20 60 100 140 180 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) v ds =5v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 20 40 60 80 100 120 140 total gate charge---qg(nc) v gs , gate-source voltage(v) v ds =40v i d =20a maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 100 s 10 s r ds( on) limit t c =25c, tj=175c, v gs =10v,r jc =0.45c/w single pulse maximum drain current vs case temperature 0 20 40 60 80 100 120 140 160 180 200 0 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =0.45c/w package limit silicon limit
cystech electronics corp. spec. no. : c918e3 issued date : 2013.06.10 revised date : page no. : 6/8 MTE05N08E3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 50 100 150 200 250 300 350 0246810 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse maximum power dissipation 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) peak transient power (w) t j(max) =175c t c =25c ja =0.45c/w transient thermal response curves 0.01 0.1 1 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =0.45 c/w
cystech electronics corp. spec. no. : c918e3 issued date : 2013.06.10 revised date : page no. : 7/8 MTE05N08E3 cystek product specification recommended wave soldering condition peak temperature soldering time product pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c918e3 issued date : 2013.06.10 revised date : page no. : 8/8 MTE05N08E3 cystek product specification to-220 dimension *: typical millimeters inches millimeters inches marking: cys e05n08 1 2 3 device name date code style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-220 plastic package cystek package code: e3 dim min. max. min. max. dim min. max. min. max. a 4.470 4.670 0.176 0.184 e1 12.060 12.460 0.475 0.491 a1 2.520 2.820 0.099 0.111 e 2.540* 0.100* b 0.710 0.910 0.028 0.036 e1 4.980 5.180 0.196 0.204 b1 1.170 1.370 0.046 0.054 f 2.590 2.890 0.102 0.114 c 0.310 0.530 0.012 0.021 h 0.000 0.300 0.000 0.012 c1 1.170 1.370 0.046 0.054 l 13. 400 13.800 0.528 0.543 d 10.010 10.310 0.394 l1 3.560 3.960 0.140 0.156 0.406 e 8.500 8.900 0.335 0.350 3.735 3.935 0.147 0.155 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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